POST_DIV_SELECT=POST_DIV_SELECT_0, BYPASS_CLK_SRC=REF_CLK_24M
Analog Audio PLL control Register
| DIV_SELECT | This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. |
| POWERDOWN | Powers down the PLL. |
| ENABLE | Enable PLL output |
| BYPASS_CLK_SRC | Determines the bypass source. 0 (REF_CLK_24M): Select the 24MHz oscillator as source. 1 (CLK1): Select the CLK1_N / CLK1_P as source. |
| BYPASS | Bypass the PLL. |
| PFD_OFFSET_EN | Enables an offset in the phase frequency detector. |
| POST_DIV_SELECT | These bits implement a divider after the PLL, but before the enable and bypass mux. 0 (POST_DIV_SELECT_0): Divide by 4. 1 (POST_DIV_SELECT_1): Divide by 2. 2 (POST_DIV_SELECT_2): Divide by 1. |
| LOCK | 1 - PLL is currently locked. 0 - PLL is not currently locked. |